1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device, and more particularly to a random access memory (DRAM) device with improved layouts of bit lines and sense amplifiers.
2. Description of the Related Art
Improvement of memory cell structures and advancement of the microfabrication technique have remarkably increased an integration density of the DRAM whose memory cells consist of one transistor and one capacitor. In reading out data from a memory cell array of the DRAM, the data from the cell array is applied through paired bit lines to a sense amplifier. The data is amplified by the sense amplifier and then outputted from the memory device. At present, many companies competitively develop the DRAMs of 16 mega bits. In the case of the DRAM of such a high integration density, memory cell size, bit line width, and bit line pitch are extremely small. The active element, or MOS transistor, contained in the sense amplifier is limited in reducing its size, because the element characteristic and the required processing accuracy must be secured. The limit of the element size reduction makes it difficult to lay out the sense amplifiers in connection with the bit line pairs.
A conventional sense amplifier is of the flip-flop type in which a plurality of MOS transistors are connected between paired bit lines. The source common to two MOS transistors is connected to a sense amplifier activating circuit through a control line. To operate the sense amplifier, a source potential is controlled through the control line in an active mode.
Usually, in connection with the bit line pairs, a dynamic sense amplifier is formed by combining two types of sense amplifiers, a sense amplifier (NMOS sense amplifier) using n-channel MOS transistors and another sense amplifier (PMOS sense amplifier) using p-channel MOS transistors. The NMOS sense amplifier is for amplifying a minute potential difference between the paired bit lines, viz., a low potential. The PMOS amplifier is for amplifying the amplified potential difference up to a maximum amplitude, viz., a high potential. These types of sense amplifiers, NMOS and PMOS, are each constructed with a flip-flop using a couple of MOS transistors, and the circuit arrangements of them are the same.
In the layout of the conventional DRAM, a single MOS transistor is connected to respective ones of a pair of bit lines such that the drain and gate thereof are connected to respective ones of the parallel bit lines and the source is connected to a control line. In such a layout, where the bit line width and the bit line pitch are extremely narrow, e.g, 0.5 .mu.m, the size of the MOS transistor per se and the contact regions must be correspondingly extremely small. However, there is a limit in reducing the size of them for the above reason, guaranteeing the element characteristics and the required processing accuracy.
There is known a divided sense amplifier system in which a sense amplifier is divided into a plurality of sense amplifiers. In this system, however, two n-wells are required for a single memory cell array, to divide the PMOS sense amplifier into two groups. The well separation consumes a large chip area. Particularly in the case of a large capacity DRAM, to secure a high speed operation, it is necessary to divide the memory cell array into 8 to 16 blocks in the bit line direction. Use of the two n-wells every divided cell array greatly hinders improvement of an integration density.
As described above, the conventional layout of the sense amplifier section of the DRAM does not result in a further increase of the integration density.